Semiconductor technologies are continually progressing to smaller feature sizes, for example down to feature sizes of 65 nanometers, 45 nanometers, and below. A patterned photoresist (resist) layer used to produce such small feature sizes typically has a high aspect ratio and maintaining a desired critical dimension (CD) can be very difficult, especially for a resist layer with a high aspect ratio. Double patterning processes have been introduced to form various features with smaller dimensions. However, conventional double patterning processes involve multiple etching processes with high manufacturing cost and low throughput.